28F800F3 datasheet(13/47 Pages) INTEL

13 / 47 page

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PRODUCT PREVIEW

3.1.5

RESET

The device enters a reset mode when RST# is

driven low. In reset mode, internal circuitry is turned

off and outputs are placed in a high-impedance

state.

After return from reset, a time tPHQV is required until

outputs are valid, and a delay (tPHWL or tPHEL) is

required before a write sequence can be initiated.

After this wake-up interval, normal operation is

restored. The device defaults to read array mode,

the status register is set to 80H, and the read

configuration register defaults to asynchronous

page-mode reads.

If RP# is taken low during a block erase or program

operation, the operation will be aborted and the

memory contents at the aborted location are no

longer valid. See Figure 21 for detailed information

regarding reset timings.

4.0

COMMAND DEFINITIONS

Device operations are selected by writing specific

commands into the CUI. Table 3 defines these

commands.

Table 2. Bus Operations

Mode

Notes

RST#

CE#

ADV#

OE#

WE#

Address

VPP

DQ0–15

Reset

VIL

XXXXXX

High Z

Standby

VIH

XXXXX

High Z

Output Disable

VIH

VIL

XVIH

VIH

High Z

Read

1,2

VIH

VIL

VIH

DOUT

Read Identifier

Codes

VIH

VIL

VIH

See

Table 4

See

Table 4

Write

3,4

VIH

VIL

VIH

VIL

DIN

NOTES:

Refer to

DC Characteristics. When VPP

≤ VPPLK, memory contents can be read, but not altered.

X can be V

IL or VIH for control and address input pins and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK and

VPPH1/2 voltages.

Command writes involving block erase or program are reliably executed when VPP = VPPH1/2 and VCC = VCC1/2

(see Section 8 for operating conditions at different temperatures).

Refer to Table 3 for valid DIN during a write operation.

28F800F3 Datasheet(PDF) 13 Page - Intel Corporation

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