PRODUCT PREVIEW

10

AUTOMOTIVE

®

P5.3:2

P5.0

I/O

Port 5

This is a memory-mapped, bidirectional port.

Port 5 shares package pins with the following signals: P5.0/ADV#/ALE,

P5.2/WR#/WRL#/PLLEN, and P5.3/RD#. P5.1 and P5.7:4 are not implemented.

P6.7:4

P6.1:0

O

Port 6

This is a standard bidirectional port.

Port 6 shares package pins with the following signals: P6.0/EPA8/COMP0,

P6.1/EPA9/COMP1, P6.4/SC0, P6.5/SD0, P6.6/SC1, and P6.7/SD1.

PACT#

O

Programming Active

During auto programming or ROM-dump, a low signal indicates that

programming or dumping is in progress, while a high signal indicates that the

operation is complete.

PACT# is multiplexed with P2.7 and OSCOUT.

PALE#

I

Programming ALE

During slave programming, a falling edge causes the device to read a

command and address from the PBUS.

PALE# is multiplexed with P2.1 and RXD.

PBUS.15:0

I/O

Address/Command/Data Bus

During slave programming, ports 3 and 4 serve as a bidirectional port with

open-drain outputs to pass commands, addresses, and data to or from the

device. Slave programming requires external pull-up resistors.

During auto programming and ROM-dump, ports 3 and 4 serve as a regular

system bus to access external memory. P4.6 and P4.7 are left unconnected;

P1.1 and P1.2 serve as the upper address lines.

Slave programming:

PBUS.7:0 share package pins with AD7:0 and P3.7:0.

PBUS.15:8 share package pins with AD15:8 and P4.7:0.

Auto programming:

PBUS.15:8 share package pins with AD15:8 and P4.7:0; PBUS.7:0 share

package pins with AD7:0 and P3.7:0.

PLLEN

I

Phase-locked Loop Enable

This active-high input pin enables the on-chip clock multiplier.

PMODE.3:0

I

Programming Mode Select

Determines the programming mode. PMODE is sampled after a device reset

and must be static while the microcontroller is operating.

PMODE.3:0 are multiplexed with P0.7:4 and ACH7:4.

Table 4. Signal Descriptions (Continued)

Name

Type

Description