CDP1802BCEX datasheet(14/27 Pages) INTERSIL

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FIGURE 12. DMA IN CYCLE TIMING WAVEFORMS

FIGURE 13. DMA OUT CYCLE TIMING WAVEFORMS

Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued)

CLOCK

TPA

TPB

MACHINE

INSTRUCTION

DMA-IN

MRD

MWR

MEMORY

DATA BUS

CYCLE

OUTPUT

NOTE 1

MEMORY READ CYCLE

MEMORY READ, WRITE

MEMORY WRITE CYCLE

OR NON-MEMORY CYCLE

“DON’T CARE” OR INTERNAL DELAYS

HIGH IMPEDANCE STATE

(NOTE 1)

USER GENERATED SIGNAL

VALID DATA FROM INPUT DEVICE

CYCLE n

FETCH (S0)

CYCLE (n+1)

EXECUTE (S1)

CYCLE (n+2)

DMA (S2)

VALID OUTPUT

01234567012345670123456

CLOCK

TPA

TPB

MACHINE

CYCLE

INSTRUCTION

DMA OUT

MRD

MWR

MEMORY

OUTPUT

DATA

STROBE

(S2

• TPB)

CYCLE n

CYCLE (n + 1)

CYCLE (n + 2)

DMA (S2)

EXECUTE (S1)

FETCH (S0)

VALID OUTPUT

VALID DATA FROM MEMORY

NOTE 1

MEMORY READ CYCLE

MEMORY READ, WRITE

MEMORY READ CYCLE

OR NON-MEMORY CYCLE

“DON’T CARE” OR INTERNAL DELAYS

HIGH IMPEDANCE STATE

USER GENERATED SIGNAL

(NOTE 1)

CDP1802A, CDP1802AC, CDP1802BC

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