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CDP1802BCEX Datasheet(PDF) 27 Page - Intersil Corporation |
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CDP1802BCEX Datasheet(HTML) 27 Page - Intersil Corporation |
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27 / 27 page ![]() 3-29 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Operating and Handling Considerations Handling All inputs and outputs of Intersil CMOS devices have a net- work for electrostatic protection during handling. Operating Operating Voltage - During operation near the maximum supply voltage limit care should be taken to avoid or suppress power supply turn-on and turn-off transients, power supply rip- ple, or ground noise; any of these conditions must not cause VDD - VSS to exceed the absolute maximum rating. Input Signals - To prevent damage to the input protection circuit, input signals should never be greater than VDD nor less than VSS. Input currents must not exceed 10mA even when the power supply is off. Unused Inputs - A connection must be provided at every input terminal. All unused input terminals must be connected to either VDD or VSS, whichever is appropriate. Output Short Circuits - Shorting of outputs to VDD or VSS may damage CMOS devices by exceeding the maximum device dissipation. S1 F 8 LDl MRP → D; RP + 1 → RP MRP RP 0 1 0 Fig. 8 9 ORl MRP OR D → D; RP + 1 → RP A ANl MRP AND D → D; RP + 1 → RP B XRl MRP XOR D → D; RP + 1 → RP C ADl MRP + D → DF, D; RP + 1 → RP D SDl MRP - D → DF, D; RP + 1 → RP F SMl D - MRP → DF, D; RP +1 → RP E SHL MSB(D) → DF; 0 → LSB(D) Float RP 1 1 0 Fig. 6 S2 DMA IN BUS → MR0; R0 + 1 → R0 Data from I/O Device R0 1 0 0 6, Fig. 12 DMAOUT MR0 → BUS; R0 + 1 → R0 MR0 R0 0 1 0 6, Fig. 13 S3 INTERRUPT X, P → T; 0 → lE, 1 → P; 2 → X Float RN 1 1 0 Fig. 14 S1 LOAD IDLE (CLEAR, WAlT = 0) M(R0 - 1) R0 - 1 0 1 0 5, Fig. 8 NOTES: 1. lE = 1, TPA, TPB suppressed, state = S1. 2. BUS = 0 for entire cycle. 3. Next state always S1. 4. Wait for DMA or INTERRUPT. 5. Suppress TPA, wait for DMA. 6. IN REQUEST has priority over OUT REQUEST. 7. See Timing Waveforms, Figure 5 through Figure 14 for machine cycles. TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) STATE I N SYMBOL OPERATION DATA BUS MEMORY ADDRESS MRD MWR N LINES NOTES CDP1802A, CDP1802AC, CDP1802BC |
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