3-28

S1

7

9

MARK

(X, P)

→ T, MR2; P → X;

R2 - 1

→ R2

T

R2

1

0

0

Fig. 7

A

REQ

0

→ Q

Float

RP

1

1

0

Fig. 6

B

SEQ

1

→ Q

Float

RP

1

1

0

Fig. 6

C

ADCl

MRP + D + DF

→ DF, D;

RP + 1

MRP

RP

0

1

0

Fig. 8

D

SDBl

MRP - D - DFN

→ DF, D;

RP + 1

MRP

RP

0

1

0

Fig. 8

E

SHLC

MSB(D)

→ DF; DF → LSB(D)

Float

RP

1

1

0

Fig. 6

F

SMBl

D - MRP - DFN

→ DF, D;

RP + 1

MRP

RP

0

1

0

Fig. 8

8

0 - F

GLO

RN.0

→ D

RN.0

RN

1

1

0

Fig. 6

9

0 - F

GHl

RN.1

→ D

RN.1

RN

1

1

0

Fig. 6

A

0 - F

PLO

D

→ RN.0

D

RN

1

1

0

Fig. 6

B

0 - F

PHI

D

→ RN.1

D

RN

1

1

0

Fig. 6

S1#1

C

0 - 3,

8 - B

Long Branch

Taken: MRP

→ B; RP + 1 →

RP

MRP

RP

0

1

0

Fig. 9

#2

Taken: B

→ RP.1;

MRP

→ RP.0

M(RP + 1)

RP + 1

0

1

0

Fig. 9

S1#1

Not Taken: RP + 1

→ RP

MRP

RP

0

1

0

Fig. 9

#2

Not Taken: RP + 1

→ RP

M(RP + 1)

RP + 1

0

1

0

Fig. 9

S1#1

5

6

7

C

D

E

F

Long Skip

Taken: RP + 1

→ RP

MRP

RP

0

1

0

Fig. 9

#2

Taken: RP + 1

→ RP

M(RP + 1)

RP + 1

0

1

0

Fig. 9

S1#1

Not Taken: No Operation

MRP

RP

0

1

0

Fig. 9

#2

Not Taken: No Operation

MRP

RP

0

1

0

Fig. 9

S1#1

4

NOP

No Operation

MRP

RP

0

1

0

Fig. 9

#2

No Operation

MRP

RP

0

1

0

Fig. 9

S1

D

0 - F

SEP

N

→ P

NN

RN

1

1

0

Fig. 6

E

0 - F

SEX

N

→ X

NN

RN

1

1

0

Fig. 6

S1

F

0

LDX

MRX

→ D

MRX

RX

0

1

0

Fig. 8

1

2

3

4

5

7

OR

AND

XOR

ADD

SD

SM

MRX OR D

→ D

MRX AND D

→ D

MRX XOR D

→ D

MRX + D

→ DF, D

MRX - D

→ DF, D

D - MRX

→ DF, D

MRX

RX

0

1

0

Fig. 8

6

SHR

LSB(D)

→ DF; 0 → MSB(D)

Float

RX

1

1

0

Fig. 6

TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)

STATE

I

N

SYMBOL

OPERATION

DATA

BUS

MEMORY

ADDRESS

MRD

MWR

N

LINES

NOTES

CDP1802A, CDP1802AC, CDP1802BC