CDP1802BCEX datasheet(20/27 Pages) INTERSIL

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suppressed during the initialization cycle. The next cycle is an

S0, S1, or an S2 but never an S3. With the use of a 71 instruc-

tion followed by 00 at memory locations 0000 and 0001, this

feature may be used to reset IE, so as to preclude interrupts

until ready for them. Power-up reset can be realized by con-

necting an RC network directly to the CLEAR pin, since it has a

Schmitt triggered input, see Figure 24.

Pause

Stops the internal CPU timing generator on the ﬁrst negative

high-to-low transition of the input clock. The oscillator contin-

ues to operate, but subsequent clock transitions are ignored.

Run

May be initiated from the Pause or Reset mode functions. If

initiated from Pause, the CPU resumes operation on the ﬁrst

negative high-to-low transition of the input clock. When initi-

ated from the Reset operation, the ﬁrst machine cycle follow-

ing Reset is always the initialization cycle. The initialization

cycle is then followed by a DMA (S2) cycle or fetch (S0) from

location 0000 in memory.

Run-Mode State Transitions

The CPU state transitions when in the RUN and RESET

modes are shown in Figure 25. Each machine cycle requires

the same period of time, 8 clock pulses, except the initializa-

tion cycle, which requires 9 clock pulses. The execution of

an instruction requires either two or three machine cycles,

S0 followed by a single S1 cycle or two S1 cycles. S2 is the

response to a DMA request and S3 is the interrupt response.

Table 2 shows the conditions on Data Bus and Memory

Address lines during all machine states.

Instruction Set

The CPU instruction summary is given in Table 1. Hexadeci-

mal notation is used to refer to the 4-bit binary codes.

In all registers bits are numbered from the least signiﬁcant

bit (LSB) to the most signiﬁcant bit (MSB) starting with 0.

R(W): Register designated by W, where

W = N or X, or P

R(W).0: Lower order byte of R(W)

R(W).1: Higher order byte of R(W)

Operation Notation

M(R(N))

→ D; R(N) + 1 → R(N)

This notation means: The memory byte pointed to by R(N) is

loaded into D, and R(N) is incremented by 1.

CLEAR

VCC

CDP1802

THE RC TIME CONSTANT

SHOULD BE GREATER THAN

THE OSCILLATOR START-UP

TIME (TYPICALLY 20ms)

FIGURE 24. RESET DIAGRAM

FIGURE 25. STATE TRANSITION DIAGRAM

S2 DMA

S1 RESET

S1 EXECUTE

S0 FETCH

S3 INT

S1 INIT

DMA

• INT

DMA

IDLE

• DMA • INT

FORCE S1

(LONG BRANCH,

DMA

• IDLE • INT

DMA

INT

• DMA

LONG SKIP, NOP, ETC.)

PRIORITY: FORCE S0, S1

DMA IN

DMA OUT

INT

• DMA

CDP1802A, CDP1802AC, CDP1802BC

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