2-23

Using the built-in 12pF integration capacitor across the error

amplifier, the transfer function, G(s) for the lead-lag network is:

The HIP5020 design and simulation software (available at

the Harris WEB site) computes these values and greatly

simplifies the following compensation design process. To

design a DC-DC converter for stable operation:

1. Determine the output capacitor’s ESR zero frequency,

2. Place the compensation pole (

3. Determine the desired converter bandwidth (or the fre-

quency where the loop gain is unity). Bandwidth must be

below 1/2 the switching frequency. A reasonable band-

width is approximately 1/10 the switching frequency.

4. Select the compensation zero (

bandwidth frequency and adjust as necessary to achieve

5. Adjust the gain (via R1) and iterate the compensation zero

and gain as needed to achieve the desired bandwidth

and phase margin.

6. Measure the closed-loop transfer function at both mini-

mum and maximum input voltage and at both full load

and the Run-to-Hysteretic mode load current boundary.

Be sure to note the phase margin and the gain margin.

The single component R1 can compensate the control loop if

the detailed characteristics of the output capacitor, bandwidth,

and switching frequency meet strict requirements. The

bandwidth (or unity gain frequency) must be much greater

the switching frequency. Additionally the break frequency of

output capacitor’s ESL must be much greater than the

switching frequency. If these conditions exist, the ESR zero

provides the necessary phase boost. However, note that the

ESR is not a well controlled parameter and is variable with

temperature and aging. Select R1 for the proper

compensation gain and confirm the selection with closed-loop

measurements. Additionally determine the worst case ESR

variation and estimate this effect on converter stability.

Output Voltage Setting

The resistor divider R1 and R2 sets the output voltage as a

function of the reference voltage. Select R1 to achieve the

desired bandwidth then determine R2 from:

The output voltage regulation improves with the use of

integrated resistor network. By integrating the resistors, the

variations of R1 track the variations of R2. The ratio of R1 to

R2 remains constant and this minimizes the output voltage

variation to improve regulation. Integrated resistor networks

are available in small SOT-23 packages such as the one

used in Circuit 2.

Slope Compensation

Slope compensation is necessary to avoid current loop

instability for duty ratios above 50%. Select C7 to set the

amount of slope compensation according to the following:

This value of capacitance provides a compensation ramp that is

1/2 of the reflected output inductor decreasing current slope.

Charge Pump and Bootstrap Design

The charge pump and bootstrap circuit supply the internal

bias power for the HIP5020. The majority of the bias power

goes to gate drives. The charge pump operates at the

switching frequency for input voltage below 9.8V. Select

The gate of the upper N-Channel MOSFET is driven above

the input voltage by the internal gate drive with power

supplied by the bootstrap circuit D1 and C3. A fast recovery,

low leakage diode is recommended for D1. C3 should be a

high quality ceramic capacitor.

Hysteretic Mode Current Setting

The voltage on the HMI pin sets the load current boundary

between Run mode and Hysteretic mode. This setting

enables the designer to trade-off efficiency and output

voltage ripple at low output current. The output voltage ripple

is higher in Hysteretic mode as compared with Run mode.

Many systems can tolerate higher power supply ripple at

light loads because the reduced load induced ripple. The

designer should select the load current boundary based

upon converter efficiency characteristics and known load

characteristics. For example, a HIP5020 converter powering

a microprocessor load might select the HMI boundary

between the sleep and active states of operation.

The ripple voltage is highest for load current just below the

mode boundary. The ripple voltage is a function of the

hysteresis width, the resistors R1 and R2, the hysteretic

current setting (HMI) and the output capacitor ESR as

described in the Hysteretic Mode section.

Figure 9 shows the efficiency versus load for two different

with a higher settings. The efficiency at light load current is

Gs

()

K

s

----

1s

ω

z

⁄

+

1s

ω

p

⁄

+

------------------------

•

=

where K

1

R1

12

10

12

–

•

•

-----------------------------------------

=

ω

z

1

R1

R6

+

() C9

•

-----------------------------------------

=

and

ω

p

1

R6

C9

•

----------------------

=

12

π C1 ESR

•

•

•

()

⁄

R2

R1

1.26

V

O

1.26

–

--------------------------

•

=

C7

MAX

L1

272

10

6

–

•

•

V

O

-----------------------------------------

=

C4 C5

MIN

,

0.088

F

S

---------------

0.12

10

6

–

•

+

=

HIP5020