7-64

HIP5061

Typical Application Circuit

Figure 33 shows a Simplified Block Diagram of the HIP5061 in a

regulator. The Gate Driver supply is decoupled from the main

digital circuitry. A Schottky diode insures efficient energy transfer

from the DMOS drain circuit inductor to the load. To set the

output voltage, two resistors are used to scale the output supply

voltage down to the 5.1V internal reference.

The heart of the IC is the high current DMOS power

transistor with its associated gate driver and high-speed

peak current control loop. A portion of the converters DC

output is applied to a transconductance error amplifier that

compares the fed back signal with the internal 5.1V

reference. The output of this amplifier is brought out at

compensation of the control loop. This same signal is also

applied internally to program the peak DMOS transistor

drain current. To assure precise current control, the

response time of this peak current control loop is less

than 50ns.

A 2MHz internal clock provides all the timing signals for the

converter operating at 250kHz. A slope compensation circuit

is also incorporated within the converter IC to eliminate sub-

harmonic oscillation that occurs in continuous-current mode

converters operating with duty cycles greater than 50%.

HIP5061 Description of Operation

Figure 2 shows a more detailed Functional Block Diagram of

the HIP5061. An internal 14V shunt regulator in conjunction

with an external series resistor provides internal operating

voltage to the IC in applications where no 12V auxiliary sup-

ply is available. Note that In applications where the input

regulator is shown as a zener diode on the diagrams of Fig-

ure 2 and Figure 33.

The 2MHz clock is processed in the Control Logic block to

provide various timing signals. A cycle of operation begins

when a 100ns pulse (which occurs at a 4

µs interval) triggers

the latch that initiates the DMOS transistor on-time. This

pulse also provides a blanking interval in the Current Moni-

toring block to eliminate false turn-offs caused by high tran-

sient pulse currents that occur during turn-on. The output of

FIGURE 33. SIMPLIFIED BLOCK DIAGRAM OF THE HIP5061 IN A TYPICAL "BOOST" CONFIGURATION

SLOPE

COMPENSATION

5.1V

REFERENCE

GATE

DRIVER

CONTROL

LOGIC

HIP5061

2MHz

OVER

TEMP

UNDER

VOLTAGE

V/I

AMP

FB

GND

DRAIN

(SOURCE)

2.6V

TAB

CLOCK