HIP5061 datasheet(13/20 Pages) INTERSIL

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7-65

HIP5061

the Current Ramp block is summed with the sensed DMOS

transistor current (to provide slope compensation) before

being compared with the Error Current signal.

The current

ramp, -0.45A/

µs, is inhibited for the ﬁrst 1.5µs (37.5%) of the

duty cycle by the Ramp Enable signal, since ramp is not

needed for slope compensation during this interval. Inhibit-

ing of the compensating ramp has the effect of reducing the

peak short-circuit current.

The output of the power supply is divided down and

monitored at the FB terminal. A transconductance error

ampliﬁer compares the DC level of the fed back voltage with

an internal bandgap reference, while providing voltage loop

compensation

means

external

resistors

and

capacitors. The Error Ampliﬁer output (the error voltage) is

then converted into a current (the Error Current) that is used

to program the required peak DMOS transistor current that

produces the desired output voltage. When the sum of the

sensed DMOS transistor current and the compensating

ramp exceed the Error Current signal, the latch is reset and

the DMOS transistor is turned off. Current comparison

around this loop takes place in less than 50ns, allowing for

excellent 250kHz converter operation. The latch can also be

reset by an under-voltage (VDD < 10.3V typical), over

temperature (TJ > +125

oC typical) or a shutdown signal

externally applied at the VC terminal. See Figure 36.

Note that if the error voltage (at the VC pin) is less that

2.55V, then the output of the Voltage-to-Current Converter

will be held at zero. This condition will produce the minimum

possible pulse width, typically 150ns (100ns blanking pulse

plus 50ns delay). Error voltages lower than this 2.55V level

will not produce shorter pulse widths. Under very light loads

(when VC goes below 1.5V), the Enable Comparator will

temporarily hold-off the PWM latch (and the DMOS transis-

tor) until the VC voltages rises above 1.5V. This low VC

inhibit circuit results in a burst-mode of operation that main-

tains regulation under light or no loads.

During an over-current condition, the output of the Error

Ampliﬁer will attempt to exceed the 7.0V threshold. At this

point, the Short-Circuit Comparator will pull down on this sig-

nal and induce a low-level oscillation about the threshold,

serving to clamp the peak error voltage. This clamping

action, in turn, will limit the peak current in the DMOS tran-

sistor, reducing the duty ratio of the switch as the demand for

current continues to increase. This action, in conjunction

with the Thermal Monitor, serves to protect the IC from over-

current (short-circuit) conditions.

Using the Transconductance Error Ampliﬁer

A transconductance ampliﬁer with a typical gm of 30mS is

used as the input gain stage where the power supply output

voltage is compared with the internally generated 5.1V

reference voltage. A PNP transistor input structure allows

this ampliﬁer to accommodate large negative going transient

voltages without causing ampliﬁer phase reversal, often

associated with PNP input structures. Negative transients up

to 5V applied to the input though at least 5.1k will not result

in phase reversal. The ampliﬁer output stage has the

customary drain to drain output to help improve the output

impedance, ideally inﬁnity. The ampliﬁer gain is typically

50dB and is not signiﬁcantly altered when operating into the

stages that follow within the IC. To minimize the output stage

idling current, while providing high peak currents to insure

rapid response to load and input transients, a class B type of

output stage was used in the ampliﬁer. Placing a 100k

resistor from the ampliﬁer output terminal, VC, to ground will

bias the output stage to an active state and still minimize

power consumption. In all cases, the resistor shunting the

transconductance ampliﬁer output must be greater than

10k

Ω to insure that the output will rise sufﬁciently high to

obtain the maximum DMOS transistor drain current.

Start-Up Sequence

Upon initial power up of the HIP5061 in a typical application

circuit, the voltage at VC will be zero, and the DMOS transis-

tor will be off. When the voltage at VDD rises above the

10.3V typical threshold, the error ampliﬁer output is enabled

and the VC voltage begins to rise in response to the low volt-

age at the FB terminal. When the VC voltage rises above

1.5V the DMOS transistor begins to switch at the minimum

duty cycle, and when it rises above 2.55V the duty cycle

begins to increase. The VC voltage (and peak DMOS tran-

sistor current) will then continue to rise until the voltage loop

gains control and establishes regulation. Note that the rate

of rise in the VC voltage can be controlled by an external soft

start circuit (See Soft Start Implementation).

If the VC voltage is unrestricted in its rate of rise, then it will

typically rise quickly to its maximum (peak current) value,

causing the DMOS transistor to turn-on and stay on until it

reaches the peak current value. At this point, the DMOS

transistor begins switching, and the VC voltage (and peak

DMOS transistor current) will drop down to the level com-

manded by the voltage loop.

Using the Shunt Regulator

The internal 14V shunt regulator in conjunction with an

external series resistor allows the IC to operate from quite

high input voltages, limited only by power dissipation in the

external resistor. When only higher voltages are available, a

bootstrap or other 12V auxiliary supply can be used to elimi-

nate this dissipation. The series resistor should be chosen to

be as large as possible to reduce power dissipation at high

line, while ensuring adequate VDD voltage at low line. The

maximum value for this resistor,

R, is given by:

Where VI is the input voltage to the power supply. The value

chosen for this resistor must also result in a current,

I, into

the VDD clamp that is less than 105mA when the input volt-

age is at its maximum:

MAX Ω

()

I MIN

10.5

–

0.033

-----------------------------------------

MAX

()

I MAX

13.3

–





MAX

--------------------------------------------------

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