4

Serial Interface Timing

NUMBER

SYMBOL

PARAMETERS

MIN

TYP

MAX

UNITS

-

-

Operating Frequency

2

8

12

MHz

-

-

Input CLK Duty Cycle

40

50

60

%

(1)

SCK Cycle Time

-

1.0

-

MHz

(2)

SACTIVE Lead Time

Before Status/Control Transfer

450

750

850

ns

Before Data Transfer

1150

1225

1300

ns

(3)

SACTIVE Lag Time

After Status/Control Transfer

650

750

850

ns

After Data Transfer

1250

1300

1400

ns

(4)

Clock (SCK) HIGH Time

450

500

550

ns

(5)

Clock (SCK) LOW Time

450

500

550

ns

(6)

Required Data In Setup Time (SIN to SCK)

-

10

50

ns

(7)

Required Data In Hold Time (SIN after SCK)

-

-10

40

ns

(8)

Data Active from High Impedance Delay (SACTIVE to SOUT Active)

-10

10

-

ns

(9)

Data Active to High Impedance Delay (SACTIVE to SOUT High

Impedance)

-10

40

ns

(10)

375

475

-

ns

(11)

Data Out Hold Time (SOUT after SCK)

375

475

-

ns

(12)

15

75

150

ns

(13)

725

75

ns

(14)

Required STAT Pulse Width

-

20

75

ns

(15)

Required RDY Pulse Width

-

20

75

ns

Required RESET Pulse Width

-

20

75

ns

(16)

1150

1750

2450

ns

SACTIVE Delay from STAT (FTU = 0)

5

285

900

ns

(17)

Required RDY Removal Time Prior to Last SCK for Short RDY

-

25

100

ns

(18)

Required RDY Hold Time after Last SCK for Long RDY

-

0

100

ns

(19)

Required SERIAL Recovery Time (Minimum Time after SACTIVE

Until Next RDY/STAT)

-

675

750

ns

Slow clock detect frequency limit

20

80

200

KHz

NOTE:

the requirements of the HIP7010. If a “Required” pulse width is specified as 75ns maximum, that implies that 75ns is the maximum width

that any HIP7010 device will require. Therefore, a system that provides a minimum pulse width of 75ns will satisfy this maximum

requirement.

HIP7010