5

Functional Pin Description

This section provides a description of each of the 14 pins of

the HIP7010 as shown in Figure 2.

the negative supply.

CLK (Clock - Input)

The Clock input (CLK) provides the basic time base refer-

ence for all J1850 symbol detection and generation. Serial

Bus transfers between the HIP7010 and the Host microcon-

troller are also timed based on the Clock input. Proper VPW

symbol detection and generation requires a 2MHz clock

which is internally derived from the CLK input. Various CLK

input frequencies can be accommodated via the Divide

Select bits in the Status/Control Register (see Status/Con-

trol Register for details).

An internal Slow Clock Detect circuit monitors the CLK input

signal and generates a HIP7010 reset if the clock is inactive

blocking the J1850 and Serial busses in the event of a clock

failure. The Slow Clock Detect reset can also be intentionally

invoked by externally inhibiting CLK input transitions.

Power can be reduced under Host control via the PowerDown

bit in the Status/Control Register (see Status/Control Regis-

ter for details). Setting the Power-Down bit effectively stops

internal clocking of the HIP7010.

(OUTPUT)

SCK

(OUTPUT)

SIN

(INPUT)

SOUT

(OUTPUT)

D7I

D6I

D0I

D7O

D6O

D0O

(6)

(11)

(8)

(5)

(12)

(13)

(1)

(4)

(7)

SACTIVE

(INPUT)

RDY (LONG)

(INPUT)

RDY (SHORT)

STAT

(INPUT)

(2)

(10)

(9)

(3)

(14)

(15)

(16)

(17)

(18)

(19)

FIGURE 1. SERIAL INTERFACE TIMING DIAGRAM

NOTES:

2. All timings assume proper CLK frequency and Divide Select values to generate 1MHz SCK.

IDLE

VPWIN

VPWOUT

RESET

TEST

SACTIVE

RDY

STAT

CLK

SIN

SOUT

SCK

1

2

3

4

5

6

7

14

13

12

11

10

9

8

FIGURE 2. 14 PIN DIP AND SO TERMINAL ASSIGNMENTS

HIP7010