HMP8191 datasheet(12/32 Pages) INTERSIL

12 / 32 page

Macrovision

The HMP8191 provides the copy protection system speciﬁed

by the Macrovision Antitaping Process for Digital Platforms

document, revision 7.01, September 6, 1996.

The device is protected by U.S. patent numbers 4,631,603,

4,577,216, and 4,819,098 and other intellectual property

rights. The use of Macrovision’s copy protection technology

in the device must be authorized by Macrovision and is

intended for home and other limited pay-per-view uses only,

unless otherwise authorized in writing by Macrovision.

Reverse engineering or disassembly is prohibited.

Additional information about Macrovision in the HMP8191 is

available to Macrovision Authorized Buyers only. Tech Brief

359, HMP8171/HMP8173 Macrovision Registers provides the

details required. Although written for the HMP8171/HMP813

encoders, the tech brief also applies to the HMP8191.

Analog Outputs

The HMP8190/HMP8191 converts the video data into

analog signals using three 10-bit DACs running at the CLK2

rate. The DACs output a current proportional to the digital

data. The full scale output current is determined by the

reference voltage VREF and an external resistor RSET. The

full scale output current is given by:

VREF must be chosen such that it is within the part’s

operating range; RSET must be chosen such that the

maximum output current is not exceeded. These limits are

listed in the Electrical Speciﬁcations section below.

If the VREF pin is not connected, the HMP8190/HMP8191

uses the internal reference voltage. Otherwise, the applied

voltage overdrives the internal reference. If an external

reference is used, it must decoupled from any power supply

noise. An example external reference circuit is shown in the

Applications section.

The HMP8190/HMP8191 generates 1VP-P nominal video

signals across 37.5

Ω loads, corresponding to doubly

terminated 75

Ω lines. The encoder may also drive larger

loads. The full scale output current and load must be chosen

such that the maximum output voltage is not exceeded.

The HMP8190/HMP8191 provides composite with S-video

output mode. The encoder outputs luminance, modulated

chrominance, and composite video signals. All three outputs

are time aligned.

Output DAC Filtering

Since the DACs run at 2x the pixel sample rate, the sin(x)/x

rolloff of the outputs is greatly reduced, and there are fewer

high frequency artifacts in the output spectrum. This allows

using simple analog output ﬁlters. The analog output ﬁlter

should be ﬂat to Fs/4 and have good rejection at 3Fs/4.

Example ﬁlters are shown in the Applications section.

Power Down Modes

To reduce power dissipation, any of the four output DACs

may be turned off. Each DAC has an independent enable bit.

Each output may be disabled in the host control register.

When the power down mode is enabled, all of the DACs and

internal voltage reference are powered down (forcing their

outputs to zero) and the data pipeline registers are disabled.

The host processor may still read from and write to the

internal control registers.

Host Interfaces

Reset

The HMP8190/HMP8191 resets to its default operating mode

on power up, when the reset pin is asserted for at least four

CLK cycles, or when the software reset bit of the host control

internal registers to their reset state and deactivates the I2C

interface. After a reset cycle, the internal registers maintain

their default values until overwritten via the I2C bus.

I2C Interface

The HMP8190/HMP8191 provides a standard I2C interface

and supports fast-mode (up to 400 Kbps) transfers. The

device acts as a slave for receiving and transmitting data

only. It will not respond to general calls or initiate a transfer.

The encoder’s slave address is either 0100 000xB when the

SA input pin is low or 0100 001xB when it is high. (The ‘x’ bit

in the address is the I2C read ﬂag.)

The I2C interface consists of the SDA and SCL pins. When

the interface is not active, SCL and SDA must be pulled high

using external 4-6k

Ω pull-up resistors. The I2C clock and

data timing is shown in Figures 10 and 11.

During I2C write cycles, the ﬁrst data byte after the slave

address speciﬁes the sub address, and is written into the

address register. Only the seven LSBs of the subaddress are

used; the MSB is ignored. Any remaining data bytes in the

I2C write cycle are written to the control registers, beginning

with the register speciﬁed by the address register. The 7-bit

address register is incremented after each data byte in the

I2C write cycle. Data written to reserved bits within registers

or reserved registers is ignored.

During I2C read cycles, data from the control register

speciﬁed by the address register is output. The address

cycle. Reserved bits within registers return a value of “0”.

Reserved registers return a value of 00H.

The HMP8190/HMP8191’s operating modes are determined

by the contents of internal registers which are accessed via

the I2C interface. All internal registers may be written or read

by the host processor at any time. However, some of the bits

and words are read only or reserved and data written to these

bits is ignored.

Table 11 lists the HMP8190/HMP8191’s internal registers.

Their bit descriptions are listed in Tables 12 through 43.

FULLSCALE mA

() 3.9VREF V

() RSET kW

()

⁄

(EQ. 1)

HMP8190, HMP8191

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