Data Sheet

ADP3334

Rev. C | Page 11

Figure 9. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-8-13)

Dimensions shown in millimeters

ORDERING GUIDE

Package Description

Package Option

Branding

ADP3334ARZ

8-Lead Standard Small Outline Package [SOIC_N]

R-8

ADP3334ARZ-REEL

8-Lead Standard Small Outline Package [SOIC_N]

R-8

ADP3334ARZ-REEL7

8-Lead Standard Small Outline Package [SOIC_N]

R-8

ADP3334ACPZ-REEL7

8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

CP-8-13

LLA

ADP3334ARMZ-REEL7

8-Lead Mini Small Outline Package [MSOP]

RM-8

L1N

REVISION HISTORY

1/14—Rev. B to Rev. C

Added EPAD Note............................................................................ 3

Changes to Figure 9, Outline Dimensions .................................. 10

Changes to Ordering Guide .......................................................... 11

3/03—Rev. A to Rev. B

Edits to Specifications ...................................................................... 2

Edits to Output Voltage ................................................................... 6

Added text to Output Voltage section ........................................... 7

Added Figure 4.................................................................................. 7

Edits to Calculating Junction Temperature section ..................... 8

Renumbered Figures 5 and 6 .......................................................... 8

1/03—Rev. 0 to Rev. A

Added 8-Lead LFCSP and 8-Lead MSOP Package........Universal

Edits to product title .........................................................................1

Edits to Features.................................................................................1

Edits to Applications .........................................................................1

Edits to General Description ...........................................................1

Removed pin numbers from Figure 1.............................................1

Edits to Specifications .......................................................................2

Edits to Absolute Maximum Ratings ..............................................3

Edits to Ordering Guide ...................................................................3

Added pinouts to Pin Configurations ............................................3

Added text to Calculating Junction Temperature section ...........8

Added LFCSP Layout Considerations section ..............................8

Added Figure 5 ..................................................................................8

Updated 8-Lead SOIC Package..................................................... 10

TOP VIEW

8

1

5

4

0.30

0.25

0.20

BOTTOM VIEW

PIN 1 INDEX

AREA

SEATING

PLANE

0.80

0.75

0.70

1.55

1.45

1.35

1.84

1.74

1.64

0.203 REF

0.05 MAX

0.02 NOM

0.50 BSC

EXPOSED

PAD

3.10

3.00 SQ

2.90

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATIONS

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.50

0.40

0.30

COMPLIANT

TO JEDEC STANDARDS MO-229-WEED

PIN 1

INDICATOR

(R 0.15)

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registered trademarks are the property of their respective owners.

D02610-0-1/14(C)