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UPD16835 Datasheet(PDF) 2 Page - NEC

Part # UPD16835
Description  MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
PDF  32 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD16835 Datasheet(HTML) 2 Page - NEC

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µPD16835
2
RECOMMENDED OPERATING RANGE
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Supply voltage
VDD
2.7
5.5
V
VM
4.8
11
V
Input voltage
VIN
0VDD
V
Reference voltage
VREF
225
250
275
mV
EXP pin input voltage
VEXPIN
VDD
V
EXP pin input current
IEXPIN
100
µA
H bridge drive current
IM (DC)
-100
+100
mA
H bridge drive current
IM (pulse)Note 1
-200
+200
mA
Clock frequency (OSCIN)fCLKNote 2
3.9
4
4.2
MHz
Clock frequency amplitude
VfCLKNote 2
0.7VDD
VDD
V
Serial clock frequency (SCLK)
fSCLK
5.0
MHz
Video sync signal width
PW (VD)Note 3
250
ns
LATCH signal wait time
t (VD-LATCH)Note 4
400
ns
SCLK wait time
t (SCLK-LATCH)Note 4
400
ns
SDATA setup time
tsetupNote 4
80
ns
SDATA hold time
tholdNote 4
80
ns
Chopping frequency
foscNote 3
32
124
kHz
Reset signal pulse width
fRST
100
µs
Operating temperature
TA
-10
+70
°C
Peak junction temperature
TCH (MAX)
125
°C
Notes 1. PW
≤ 10 ms, duty ≤ 5%
2. COSC = 33 pF, VREF = 250 mV
3. fCLK = 4 MHz
4. Serial data delay (see the figure below.)
VD
LATCH
SCLK
LATCH
SCLK
SDATA
D1
D2
D3
t (VD-LATCH)
t (SCLK-LATCH)
t (SCLK-LATCH)
tsetup thold
64 clocks (8 bits
× 8 bytes)
t (SCLK-LATCH)
Ignored because LATCH is at L level.
Ignored because LATCH is at L level.
50%
50%
50%



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