Self tests for SPC564Ax core subsystem

AN3018

12/24

Doc ID 16081 Rev 2

Resource availability: the Flash module is available during this test.

There is no restriction on the number of times the test can be performed.

3.1.6

Flash margin mode

Principle: margin read is provided as a factory programming check; it can only be used at

25°C and only on a non-cycled flash. A direct read access may be performed at margin

(either margin 0 or margin 1), on unlocked blocks. The ‘Margin read’ operation makes it

possible to unbalance the sense amplifiers, so that all the read accesses reduce the margin

vs. ‘0’ (UT0.MRV = ‘0’) or vs. ‘1’ (UT0.MRV = ‘1’).

Result: the results of the margin reads can be checked by comparison with previously

stored expected data.

Resource availability: the Flash module is not available during this test.

The test can be performed only a limited number of times (up to 10 times maximum). It

should be reserved for OEM factory test and is not recommended for use in the field.

For more details on this test, please refer to device reference manual (see Section A.1:

Reference documents).

3.2

RAM self tests

Three RAM tests can be implemented:

–

RAM dormant fault test

–

RAM ECC logic verification

–

RAM address decode

3.2.1

RAM dormant fault check

Principle: bit flip events in the RAM are detected and corrected by the ECC. When a RAM

memory location is not read, bit flip events may cumulate and generate an incorrigible error.

RAM dormant fault check can be implemented by reading regularly the whole content of the

RAM using the DMA controller.

Result: in case of error, an ECC event in the RAM is generated.

Resource availability: the RAM module is available during this test.

3.2.2

RAM ECC logic

RAM ECC covers the main system RAM.

Principle: The intent is to generate errors during data write cycles, so that subsequent

reads of the corrupted address locations generate ECC events, either single-bit corrections

or double-bit incorrigible errors that are terminated with an error response. RAM ECC test is

performed through the ECSM. The ECC error generation register is a 16-bit control register

used to force the generation of single and double bit data inversions in the memories with