Self tests for SPC564Ax analog peripherals

AN3018

20/24

Doc ID 16081 Rev 2

5

Self tests for SPC564Ax analog peripherals

5.1

Oscillator self tests

The oscillator of each SPC564Ax variant can be checked with the clock quality monitor.

5.1.1

Oscillator check

Principle: use the clock quality monitor to check the crystal clock.

Result: use status bit in clock monitor to detect a loss of clock (or use interrupt).

Resource availability: the crystal clock is available during this test.

5.2

FMPLL self tests

SPC564Ax devices have 1 FMPLL.

5.2.1

FMPLL check

Principle: use the clock quality monitor to check the FMPLL.

Result: use status bit in clock monitor to detect a loss of lock (or use interrupt).

Resource availability: the FMPLL is available during this test.

5.3

eQADC self tests

SPC564Ax devices have two ADCs with their own logic, which share the same analog

supply and reference.

5.3.1

eQADC internal reference check

Principle: SPC564Ax analog multiplexers have several internal signals available for self

tests: internal bandgap, VREF/2, VREF/4, 3/4 x VREF.

Result: obtained by checking the ADC conversion result.

Resource availability: the ADC is available during this test.

5.3.2

Analog input and ADC mux check

Principle: each eQADC has its own independent analog mux. Use the two ADCs to convert

the same analog input.

Result: obtained by checking the ADC conversion result from each ADC.

Resource availability: excluding the time needed for conversion, ADC are available during

this test.

5.3.3

Analog input and ADC mux check

Principle: fault (open, short) in the ADC analog input of the differential inputs and ADC mux

can be detected by using the pull up and pull down integrated in the eQADC.