AN4173

ADC 10-bit timing configuration parameters

Doc ID 023727 Rev 3

11/22

Figure 3.

Conversion timings (configuration for sampling rate at 20 MHz)

As described in the previous paragraph, the Tconv is the sum of the Tsample and Teval plus

0.5 or 1 Tck.

On the last AD_ck cycle of evaluation phase the signal AD_last_eval_cyc has a pulse of

‘1’.After the 10th bit evaluation is ended up, a pulse of ‘1’ on AD_end_of_conversion signal

is generated from rising edge to rising edge of AD_ck to provide external logic the

acknowledgement the conversion has completed and the AD_output bus contains the

converted value.