AN4173

Application code structure

Doc ID 023727 Rev 3

13/22

Table 2.

ADC sampling and conversion timing obtained by test code

The discrepancy between the values on the RM and those from the experimental results is

due to an effective phase shift of half AD_ck between peripheral clock and AD_ck. We must

divider implemented within ADCDig. Of this 1.5 cycles, 1 is for storing the data and 0.5 due

to phase shift.

In order to measure the time needed for the ADC conversion the system timer module

(STM) was used. The STM clock frequency is set equal to the system clock frequency.

Figure 4.

STM configuration function extracted code

The system clock is set equal to the PLL frequency by the PLL init function. This function

permits to configure the PLL in order to switch from 40MHz of XOSC up to 120MHz.

Clock

(MHz)

TCK

(µs)

INPSAMP

IMPCMP

INPLATCH

ndelay

(µs)

6

0.167

4

1

0

0.5

2.53

7

0.143

4

1

0

0.5

2.10

8

0.125

5

1

0

0.5

2.03

9

0.111

5

1

0

0.5

1.81

16

0.063

9

1

0

1

1.18

20

0.050

11

1

0

1

1.175

32

0.031

17

2

1

1

1.156