AN2503

PDP Sustain circuit

13/30

Where

ωR/L) can be ignored, the equation (Equation 2) can be simply re-written as:

Equation 3

Where

If

Equation 4

Equation 4 states that an increase of the parasitic resistance causes the recovery efficiency

to be degraded. Naturally, it is necessary to reduce the parasitic resistance by designing the

circuit board optimally as well as choosing switching devices with small on-resistance and

low on-drop voltage to minimize the hard-switching stress and improve the recovery

performance. On the other hand, reduction of the inductor value produces similar results

and, thus, using a too small value of L is not desirable with respect to driving loss.

3.1.2

Positive discharge and clamping phase

Figure 15 shows both panel discharge and the camping current paths. In the first phase the

ionized gas could be represented as a non linear resistor and the peak current during this

period is higher than that during energy recovery. The worst condition is represented when

all cells in the panel must be ignited (full white screen condition), and in this case the

discharge current could be higher than 120 A for a standard definition (SD) 42-inch PDP set.

Further increase in the current value is expected in HD PDP as the number of pixels

increases.

Figure 15.

Circuit scheme – positive discharge and clamping

τ

ωR

L

-------

⎝⎠

⎛⎞

=

ω

1

LCp

-----------

⎝⎠

⎛⎞

R

2L

-------

⎝⎠

⎛⎞

2

–

=

and

V

yx

V

s

2

------

V

ON

–

⎝⎠

⎛⎞ 1e

t

τ

---

ω

cos

–

=

t

ω

1

LCp

-----------

=

’

V

yx pk

,

V

s

2

------

V

ON

–

⎝⎠

⎛⎞ 1e

πR

2

-------

C

p

L

------

–

–

=

Vs

Vs

Vs

Vset

L7

T9

T10

T8

T12

T11

-Vreset

Cp

CS1

CS2

L1

D7

D8

D6

D5

T7

D1

Vs

T3

T2

T1

T4

T6

T5

D2

D4

D3