AN2503

PDP Power Devices characteristics

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circuit is very large since it has to conduct both ER and discharge currents. Both

application since they allow the die to have very high current density and therefore reduce

the number of paralleled devices required to maintain very low voltage drop [9.], [10.], [11.],

[12.].

For path switch in T6 position, the maximum voltage stress is (Vs + Vset) / 2

≈ 300 V, while

for path switch in T5 position, the maximum voltage stress is (Vset + |Vreset|) / 2

≈ 275 V.

4.1.5

Set - reset section

The set and reset circuit applies asymmetrical AC voltage across the panel in order to

evacuate any remaining surface charge from the cells. This is usually done at the end of

each subfield (or the beginning of the next subfield), and the power devices on this circuit

operate in the linear mode. This means that the voltage drop is very large but the current

through the device is relatively low. Due to the requirement of asymmetrical Set and Reset

voltages, Power switches in the set and reset circuits have to block up to 600 V. Typical

voltage value for Set function is 400 V and for Reset function is -150 V. This means that the

maximum voltage stress for Set circuit T9 is (Vs + Vset) = 600 V while the maximum voltage

stress for reset circuit T10 is Vset + |Vreset| = 550 V.

ST offers two families of products for this section both appreciable for their ruggedness for

linear applications.

Example device is STGP10NB60S in the IGBT Planar technology [13.]:

Further examples of devices are superMESHTM devices as follows [14.], [15.].

Table 7.

Path MOSFET features

P/N

P [W]

Package

ST60NK30ZD1

300

0.045

60/240

450

Die or MAX247

STW52NK25Z

250

0.033

52/208

300

TO-247

ST75N20

200

0.028

75/300

300

ST40N20

200

0.045

40/160

160

TO220FP

Table 8.

Set – reset IGBT features

P/N

Package

STGP10NB60S

600

1.7

10

Table 9.

Set-reset MOSFET features

P/N

P [W]

Package

ST9NK70Z

700

1

7.5/30

115 W

ST14NK60Z

600

0.5

13.5/54

160 W