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UPD17231 Datasheet(PDF) 49 Page - NEC |
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UPD17231 Datasheet(HTML) 49 Page - NEC |
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49 / 92 page ![]() Data Sheet U14360EJ1V0DS00 µPD17230, 17231, 17232, 17233, 17234, 17235, 17236 49 7. INTERRUPT FUNCTIONS 7.1 Interrupt Sources µPD17236 is provided with three interrupt sources. When an interrupt has been accepted, the program execution automatically branches to a predetermined address, which is called a vector address. A vector address is assigned to each interrupt source, as shown in Table 7-1. Table 7-1. Vector Address Priority Interrupt Source Ext/Int Vector Address 1 8-bit timer Internal 0003H 2 INT pin rising and falling edges External 0002H 3 Basic interval timer Internal 0001H When more than one interrupt request is issued at the same time, the interrupts are accepted in sequence, starting from the one with the highest priority. Whether an interrupt is enabled or disabled is specified by the EI or DI instruction. The basic condition under which an interrupt is accepted is that the interrupt is enabled by the EI instruction. While the DI instruction is executed, or while an interrupt is accepted, the interrupt is disabled. To enable accepting an interrupt after the interrupt has been processed, the EI instruction must be executed before the RETI instruction. Accepting the interrupt is enabled by the EI instruction after the instruction next to the EI instruction has been executed. Therefore, no interrupt can be accepted between the EI and RETI instructions. Caution In interrupt processing, only the BCD, CMP, CY, Z, IXE flags are automatically saved to the stack by the hardware, to a maximum of three levels. Also, within the interrupt processing contents, when peripheral hardware (timer, A/D converter, etc. ) is accessed, the DBF and WR contents are not saved by the hardware. Accordingly, it is recommended that at the beginning of interrupt processing DBF and WR be saved by software to RAM, and immediately before finishing interrupt processing the saved contents be returned to thier original location. |
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