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UPD17717GC Datasheet(PDF) 71 Page - NEC |
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UPD17717GC Datasheet(HTML) 71 Page - NEC |
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71 / 408 page  71 µPD17717, 17718, 17719 Table 8-1. Peripheral Hardware Control Functions of Control Registers (4/8) Peripheral Control Register Peripheral Hardware Control Function At Reset Clock Hardware Name Address Read/ Function Set value Power- WDT CE Stop Write Symbol ON & SP reset 01 reset reset PLL PLL mode 10H R/W PLLSCNF Sets low-order bits of swallow counter Lowest bit is 0 Lowest bit is 1 UURR frequency selection 0 Fixed to “0” 0000 synthesizer PLLMD1 Sets division mode of PLL PLLMD0 PLL reference 11H R/W PLLRFCK3 Sets reference frequency of PLL FFFF frequency PLLRFCK2 selection PLLRFCK1 PLLRFCK0 PLL unlcok FF 12H R & 0 Fixed to “0” Undefined Undefined Retained Retained Reset 0 0 PLLUL Detects status of unlock FF Locked Unclocked BEEP BEEP/general- 13H R/W 0 Fixed to “0” 0000 purpose port pin 0 function selection BEEP1SEL Selects function of P1D1/BEEP1 pin General-purpose BEEP BEEP0SEL Selects function of P1D0/BEEP0 pin I/O port BEEP clock 14H R/W BEEP1CK1 Sets output frequency of BEEP1 0000 selection BEEP1CK0 BEEP0CK1 Sets output frequency of BEEP0 BEEP0CK0 Timer Basic timer 17H R & 0 Fixed to “0” 0 Retained 1 Retained 0 carry Reset 0 0 BTM0CY Detects basic timer 0 carry FF FF reset FF set Basic timer 0 18H R/W 0 Fixed to “0” 0 0 Retained Retained clock selection 0 BTM0CK1 Selects clock of basic timer 0 BTM0CK0 Timer 3 control 28H R/W TM3SEL Selects timer 3 and D/A converter D/A converter Timer 3 0 0 Retained 0 0 Fixed to “0” TM3EN Starts or stops timer 3 counter Stops Starts TM3RES Resets timer 3 counter Not affected Reset U: Undefined R: Retained 0: 1.25 kHz 1: 2.5 kHz 2: 5 kHz 3: 10 kHz 4: 6.25 kHz 5: 12.5 kHz 6: 25 kHz 7: 50 kHz 8: 3 kHz 9: 9 kHz A: 18 kHz B: Setting prohibited C: 1 kHz D: 20 kHz E: Setting prohibited F: PLL disabled 0 011 Disabled MF VHF HF 0 101 0011 4 kHz 3 kHz 200 Hz 67 Hz 0101 0011 1 kHz 3 kHz 4 kHz 6.7 kHz 0101 b3 b2 b1 b0 0011 10 Hz 20 Hz 50 Hz 100 Hz 0101 |
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