AN3308 datasheet(40/52 Pages) STMICROELECTRONICS

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First in first out (FIFO) buffer

AN3308

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Doc ID 18198 Rev 1

Table 33 represents the FIFO full status when 32 samples are stored in the buffer while

Table 34 represents the next step when the 33rd sample is inserted into FIFO and the 1st

sample is overwritten. The new oldest sample set is made available in the output registers.

When FIFO is enabled and mode is different from bypass, the LIS3DH output registers (28h

to 2Dh) always contain the oldest FIFO sample set.

9.2

FIFO registers

The FIFO buffer is managed by three different accelerometer registers, two of these allow to

enable and configure the FIFO behavior, the third provides information about the buffer

status.

9.2.1

Control register 5 (0x24)

The FIFO_EN bit in CTRL_REG5 must be set to 1 in order to enable the internal first in first

out buffer; while this bit is set, the accelerometer output registers (28h to 2Dh) don’t contain

the current acceleration value but they always contain the oldest value stored in FIFO.

Table 34.

FIFO Overrun Representation (33rd sample set stored and 1st sample

discarded)

Output

Registers

0x28h

0x29h

0x2Ah

0x2Bh

0x2Ch

0x2Dh

Xl(1)

Xh(1)

Yl(1)

Yh(1)

Zl(1)

Zh(1)

FIFO INDEx

Sample Set

FIFO(0)

Xl(1)

Xh(1)

Yl(1)

Yh(1)

Zl(1)

Zh(1)

FIFO(1)

Xl(2)

Xh(2)

Yl(2)

Yh(2)

Zl(2)

Zh(2)

FIFO(2)

Xl(3)

Xh(3)

Yl(3)

Yh(3)

Zl(3)

Zh(3)

FIFO(3)

Xl(4)

Xh(4)

Yl(4)

Yh(4)

Zl(4)

Zh(4)

...

FIFO(30)

Xl(31)

Xh(31)

Yl(31)

Yh(31)

Zl(31)

Zh(31)

FIFO(31)

Xl(32)

Xh(32)

Yl(32)

Yh(32)

Zl(32)

Zh(32)

Table 35.

FIFO enable bit in CTRL_REG5

FIFO_EN

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