AN3308 datasheet(49/52 Pages) STMICROELECTRONICS

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AN3308

First in first out (FIFO) buffer

Doc ID 18198 Rev 1

49/52

Data can be retrieved from FIFO using every reading byte combination in order to increase

the application flexibility (ex: 196 single byte reading, 32 reading of 6 bytes, 1 multiple

reading of 196 bytes, etc.).

It is suggested to read all FIFO slots in a multiple byte reading of 196 bytes (6 output

registers by 32 slots) faster than 1*ODR. In order to minimize communication between

master and slave the reading address is automatically updated by the device; it rolls back to

0x28 when register 0x2D is reached.

In order to avoid losing data, the right ODR must be selected according to the serial

communication rate available. In the case of standard I2C mode being used (max rate 100

kHz), a single sample set reading takes 830 µs while total FIFO download is about 17.57ms.

I2C speed is lower than SPI and it needs about 29 clock pulses to start communication

(Start, Slave Address, Device Address+Write, Restart, Device Address+Read) plus an

additional 9 clock pulses for every byte to read. If this suggestion were followed, the

complete FIFO reading would be performed faster than 1*ODR, this means that using a

standard I2C, the selectable ODR must be lower than 57 Hz. If a fast I2C mode is used (max

rate 400 kHz), the selectable ODR must be lower than 228 Hz.

Figure 31.

FIFO reading diagram - FTH[4:0] = 10

In Figure 31 “Rx” indicates a 6-byte reading operation and “F0*” represents a single ODR

slot stretched for diagram convenience.

AN3308 Datasheet(PDF) 49 Page - STMicroelectronics