11

LT1310

sn1310 1310fs

PACKAGE DESCRIPTIO

MSE Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1663)

Layout Hints

The high speed operation of the LT1310 demands careful

attention to board layout. You will not get advertised

performance with careless layout. Figure 6 shows the

recommended component placement for a boost

converter.

LT1310

R2

SHDN

SYNC

GND

D1

1310 F06

L1

SW

MULTIPLE VIAS

R1

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

MSOP (MSE) 0802

0.53

± 0.01

(.021

± .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 – 0.27

(.007 – .011)

TYP

0.13

± 0.076

(.005

± .003)

0.86

(.034)

REF

0.50

(.0197)

BSC

12 3 45

4.90

± 0.15

(1.93

± .006)

0.497

± 0.076

(.0196

± .003)

REF

8

9

10

7 6

3.00

± 0.102

(.118

± .004)

(NOTE 3)

3.00

± 0.102

(.118

± .004)

NOTE 4

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010)

0

° – 6° TYP

DETAIL “A”

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.2 – 3.45

(.126 – .136)

0.889

± 0.127

(.035

± .005)

RECOMMENDED SOLDER PAD LAYOUT

0.305

± 0.038

(.0120

± .0015)

TYP

2.083

± 0.102

(.082

± .004)

2.794

± 0.102

(.110

± .004)

0.50

(.0197)

BSC

10

1

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.83

± 0.102

(.072

± .004)

2.06

± 0.102

(.081

± .004)

APPLICATIO S I FOR ATIO

Figure 6. Recommended Component Placement for Boost Converter. Note Direct High Current Paths Using Wide PC Traces. Minimize

Vias at One Location Only to Avoid Introducing Switching Currents Into the Ground Plane