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LTC1664 Datasheet(PDF) 4 Page - Linear Technology

Part # LTC1664
Description  Micropower Quad 10-Bit DAC
PDF  16 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC1664 Datasheet(HTML) 4 Page - Linear Technology

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LTC1664
4
1664fa
timing characteristics The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Figure 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 4.5V to 5.5V
t1
DIN Valid to SCK Setup
l
40
ns
t2
DIN Valid to SCK Hold
l
0
ns
t3
SCK High Time
(Note 6)
l
30
ns
t4
SCK Low Time
(Note 6)
l
30
ns
t5
CS/LD Pulse Width
(Note 6)
l
80
ns
t6
LSB SCK High to CS/LD High
(Note 6)
l
30
ns
t7
CS/LD Low to SCK High
(Note 6)
l
80
ns
t8
DOUT Propagation Delay
CLOAD = 15pF (Note 6)
l
5
80
ns
t9
SCK Low to CS/LD Low
(Note 6)
l
20
ns
t10
CLR Pulse Width
(Note 6)
l
100
ns
t11
CS/LD High to SCK Positive Edge
(Note 6)
l
30
ns
SCK Frequency
(Notes 6 and 8)
l
16.7
MHz
VCC = 2.7V to 5.5V
t1
DIN Valid to SCK Setup
(Note 6)
l
60
ns
t2
DIN Valid to SCK Hold
(Note 6)
l
0
ns
t3
SCK High Time
(Note 6)
l
50
ns
t4
SCK Low Time
(Note 6)
l
50
ns
t5
CS/LD Pulse Width
(Note 6)
l
100
ns
t6
LSB SCK High to CS/LD High
(Note 6)
l
50
ns
t7
CS/LD Low to SCK High
(Note 6)
l
100
ns
t8
DOUT Propagation Delay
CLOAD = 15pF (Note 6)
l
5
150
ns
t9
SCK Low to CS/LD Low
(Note 6)
l
30
ns
t10
CLR Pulse Width
(Note 6)
l
120
ns
t11
CS/LD High to SCK Positive Edge
(Note 6)
l
30
ns
SCK Frequency
(Notes 6 and 8)
l
10
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Nonlinearity and monotonicity are defined and tested at
VCC = 5V, VREF = 4.096V, from code 20 to code 1023. See the Rail-to-Rail
Output Considerations section.
Note 3: Digital inputs at 0V or VCC.
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: VCC = VREF = 5V.
Note 6: Guaranteed by design and not subject to test.
Note 7: Measured at code 20.
Note 8: If a continuous clock is used, CS/LD timing (t7 and t9) will limit
the maximum clock frequency to 5MHz at 4.5V to 5.5V (3.85MHz at 2.7V
to 5.5V).
Note 9: Any output shorted.



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