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LTC1664 Datasheet(PDF) 6 Page - Linear Technology

Part # LTC1664
Description  Micropower Quad 10-Bit DAC
PDF  16 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC1664 Datasheet(HTML) 6 Page - Linear Technology

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LTC1664
6
1664fa
typical perFormance characteristics
Minimum VOUT vs Load Current
(Output Sinking)
Minimum Supply Headroom vs
Load Current (Output Sourcing)
|IOUT| (mA) (SINKING)
0
2
4
6
8
10
1664 G10
1400
1200
1000
800
600
400
200
0
–55°C
25°C
125°C
VCC = 5V
CODE = 0
0
2
4
6
8
10
1664 G11
1400
1200
1000
800
600
400
200
0
–55°C
25°C
125°C
VREF = 4.096V
∆VOUT < 1LSB
CODE = 1023
|IOUT| (mA) (SOURCING)
pin Functions
GND (Pin 1): System Ground.
VOUTA to VOUTD (Pins 2–5): DAC Analog Voltage Outputs.
The output range is:
0 to
1023
1024


VREF
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
DIN into the register. When CS/LD is pulled high, SCK is
disabled and data is loaded from the shift register into the
specified DAC register(s), updating the analog output(s).
CMOS and TTL compatible.
SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.
DIN (Pin 9): Serial Interface Data Input. Data on the DIN
pin is shifted into the 16-bit register on the rising edge of
SCK. CMOS and TTL compatible.
DOUT (Pin 10): Serial Interface Data Output. Data appears
on DOUT 16 positive SCK edges after being applied to DIN.
May be tied to DIN of another serial device for daisy-chain
operation. CMOS and TTL compatible.
CLR (Pin 11): Asynchronous Clear Input. All internal shift
and DAC registers are cleared to zero at the falling edge of
the CLR signal, forcing the analog outputs to zero-scale.
CMOS and TTL compatible.
NC (Pins 12–15): Make no electrical connection to these
pins.
VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.



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