DocID025506 Rev 1

9/19

AN4391

P-channel FETs in low power DC-DC converters

19

Equation 2

D is the converter duty-cycle (D=V

OUT

/V

IN

) and I the drain current. Increasing D, conduction

losses become more significant. Converter losses can be minimized only if MOSFET

dynamic (Q

G

, gate charge) and static (R

DS(on)

, drain-source resistance) parameters are as

low as possible. In

Figure 9 efficiency curves are shown:

Figure 9. Efficiency comparison

The efficiency gain is high both at light and full load, due to simultaneous switching and

conduction loss minimization. Finally,

Figure 10 shows thermal measurements at light

(I

OUT

= 0.5 A) and full load (I

OUT

= 2 A):

Figure 10. Temperature measurements

At low currents, thanks to lower intrinsic capacitances, the STL30P3LLH6 has lower

switching losses and gate drive losses (they are needed to switch on and off the device):

P

CON D

DR

DS

o n

2

⋅⋅

=

GIPG131120130934FSR

GIPG131120130936FSR