DocID025506 Rev 1

5/19

AN4391

P-channel technology overview

19

In a trench structure, the gate electrode is made up of a deep dug polysilicon electrode,

isolated by a gate oxide layer. So, the trench extends beyond the bottom of N- body region

to form a channel connecting P+ source region to P- drift region. The elimination of JFET

region, which affects negatively the R

DS(on)

planar structures, allows very competitive

R

DS(on)

values to be achieved and the cell pitch to be reduced, with additional benefits in

other R

DS(on)

components.The main electrical parameters of two MOSFETs are reported in

Table 1: the STL30P3LLH6 is realized with the new STripFET VI DeepGATE technology

and is compared with an old planar device.

In

Figure 3 there is a comparison between the R

DS(on)

x area and die-size of two above

mentioned devices:

Figure 3. STripFET VI DeepGATE technology vs. planar one

As shown in the previous chart, the STL30P3LLH6 R

DS(on)

x area improvement is around

60% (both at 4.5 V and 10 V), while its die-size is halved.

Table 1. MOSFET electrical parameters

Type

@ 250

µA

typ. @ 5 V

typ. @ 10

V

µA

V

STL30P3LLH6

> 30 V

39 m

Ω

28 m

Ω

1.8 V

1300 pF

125 pF

175 pF

2.3

Ω

Old planar

device

> 30 V

65 m

Ω

45 m

Ω

1.6 V

1350 pF

130 pF

490 pF

3

Ω

GIPG131120130900FSR