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4-MULTIPLEXED LCD WITH A STANDARD ST62

To use the LCD driver, proceed as follows:

– Before calling any LCD driver subroutine, the main routine must initialise the six display var-

iables.

– Then, it must call the LCD_Init subroutine to initialise LCD driver internal variables and to

configure segment port pins as output push-pull.

– Once the LCD_Init subroutine called, the main software must frequently call the LCD_Do

subroutine. This subroutine updates the I/O ports so as to generate the required waveforms.

The delay between two consecutive calls to LCD_Do represents the duration of 1 LCD phase,

– The six display variables can be modified at any time by the main software. Each time the

LCD_Do

subroutine is executed, it reports the changes on the waveforms, i.e. on the LCD.

– In parallel to LCD_Do calls, the main software must call the LCD_Flash subroutine. The de-

lay between two consecutive calls to LCD_Flash represents half of the flashing period.

– It is the main software that is in charge of generating a time base (generally using a timer

peripheral). This way, a single time base can be used at the same time for LCD driving, flash-

ing frequency and other application tasks.

Important notice: if delays between calls to LCD_Do are too irregular, LCD segment absolute

DC voltage can become too high, with a risk of damaging the LCD.

2.2 ADDITIONAL INFORMATION FOR CUSTOMISATION

The current LCD phase (

ϕ

driver. This variable is initialised by LCD_Init and incremented by LCD_Do, from 0 to 7 and

back to 0. To update the configuration register of the segments and commons ports, LCD_Do

uses LCD_Ph as an index to scan look-up tables.

Note: because computing the new register values takes time, LCD_Do stores the new values

in RAM buffers, and updates all the real registers at the same time. This way, transitions on

backplane and frontplane waveforms can be synchronised. This synchronisation helps

keeping a low DC voltage on LCD segments. For Data Registers, the RAM buffer used is the

shadow register.

The algorithms described in this section are designed to generate the proper backplane and

2.2.1 Generation of backplane signals

Each time LCD_Do is executed, it updates the three configuration registers (DDR, DR and OR)

of the commons port, in order to output either 0,

LCD_drv.st6

defines three constant tables giving the values of each configuration register

depending on the current LCD phase: