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4-MULTIPLEXED LCD WITH A STANDARD ST62

wave_ddr:

DB

001h,002h,004h,008h,001h,002h,004h,008h

wave_dr:

DB

00fh,00fh,00fh,00fh,00eh,00dh,00bh,007h

wave_or:

DB

001h,002h,004h,008h,001h,002h,004h,008h

When applying these values to the port registers, LCD_Do uses a mask (COM_MASK equate) to

modify only the appropriate pins. To modify the Data Register, it uses DR_com_2 shadow reg-

ister.

How to customise: it is easy to modify the pins allocation for backplane pins, as long as they

all belong to the same I/O port. You only need to change COM_MASK and the three constant ta-

bles.

2.2.2 Generation of frontplane signals

Here, LCD_Do only has to update the Data Register. But operations are more complex be-

cause of character coding.

The procedure contains four steps:

Step 1: Writing into variables that are images of min_dig0, min_dig1, hr_dig0, hr_dig1

and icons, taking flashing into account : the image variable contains either a blank value or

the content of the original variable. This image variable represents what is really to be dis-

played on the LCD. For example, if a digit displays a flashing “9”, its image variable contains

alternately '9' or 'f' (code for blank digit).

Step 2: Updating the Data shadow Register only considering the 7-segment characters. This

requires a constant table to store character coding.

Step 3: Updating the Data shadow Register taking the icons into account.

Step 4: Copying the Data shadow Register into the Data Register.

Steps 1 and 4 are independent from I/O pins allocation, so they will not be described here.

Step 2 starts by clearing the Data shadow Register for all the frontplane pins. Then, for each

7-segment digit, the cycle of operations described by Figure 8 modifies this shadow register.

Due to the mask mechanism, the ADD operation is equivalent to an OR (the ST6 instruction

set does not supply a direct OR operation).

only in phases

ϕ

all icon segments are OFF. Step 3 consists in correcting the shadow register to make sure that

all required icons are ON. To do this, it performs bit manipulation instructions with the following

bit definition equates:

ICON0_SEG

EQU

1

ICON1_SEG

EQU

3

ICON2_SEG

EQU

5

ICON3_SEG

EQU

7