µPD6376

5

2. INPUT SIGNAL FORMAT

•

Input data must be input as 2’s complement, MSB first.

2’s complement is a method of expressing both positive numbers and negative numbers as binary numbers. See

the table below.

2’s Complement

Decimal Number

L.OUT, R.OUT Pin Voltage TYP. (V)

(MSB)

(LSB)

0111

1111

1111

1111

+32767

2.6

0111

1111

1111

1110

+32766

0000

0000

0000

0001

+1

0000

0000

0000

0000

0

1.6

1111

1111

1111

1111

–1

1000

0000

0000

0001

–32767

1000

0000

0000

0000

–32768

0.6

Values differ depending on IC fabrication variations, supply voltage fluctuations, and ambient temperature.

•

Synchronize the (SI, LSI, RSI) data bit delimitations and the LRCK, WDCK reverse timing to the falling edge of

CLK.

•

CLK requires the input of 16 clocks between sample data (16 bits). Also, make the time interval for 1 bit the same

as 1 clock cycle.