µPD6376

6

2.1 Supplying Clock to CLK even outside Sample Data Interval

2.1.1 Serial data input (Pin 1 is Low or Open)

Synchronize the reverse timing of LRCK with the falling edge of CLK upon completion of LSB input (Point A in Figure

2-1).

Figure 2-1 Timing Chart for Serial Data Input

A

A

Interval of 1 sample data

LSB

CLK

SI

LRCK

16

12

34

12

34

5

6789 10 11 12 13 14 15 16

MSB

LSB

MSB

2.1.2. Inputting parallel data (Pin 1 is High)

Synchronize the timing of the falling edge of WDCK with the falling edge of CLK upon completion of LSB input of

data (LSI, RSI) (Point A in Figure 2-2.).

Figure 2-2 Parallel Data Input Timing Chart

A

A

LSB

CLK

LSI

RSI

WDCK

16

12

34

12

5

6789 10 11 12 13 14 15 16

MSB

LSB

MSB

LSB

16

12

34

12

5

6789 10 11 12 13 14 15 16

MSB

LSB

MSB