AN2038

I2C emulation

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2

I2C emulation

2.1

I2C basics

The I2C-bus has two wires, serial data (SDA) and serial clock (SCL), used to carry

information between the devices. Each device is recognized by a unique address and can

operate as either a transmitter or receiver, depending on the function of the device.

In addition to transmitters and receivers, devices can also be considered "masters" or

"slaves" when performing data transfers. A master is the device which initiates a data

transfer on the bus and generates the clock signals. At that time, any device addressed is

considered a slave.

Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a pull-

up resistor (see Figure 1). When the bus is free, both lines are HIGH. The output stages of

devices connected to the bus must have an open-drain or open-collector to perform the AND

function. Since data on the I2C-bus can be transferred at rates more than 100 kb/s in

Standard-mode, in this application we reach a speed of 4 kb/s. This is caused by need to

emulate the I2C with the SPI peripheral and the presence of a non-interruptible interrupt

sub-routine for the motor control application.

Figure 1.

I2C bus

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or

LOW state of the data line can only change when the clock signal on the SCL line is LOW

(see Figure 2).

Figure 2.

Data Valid

+VDD

SDA

SCL

DEV1

DEV2

Data Stable

Changing

allowed

Data Stable

SDA

SCL