AN2038

I2C emulation

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Figure 5.

7-bit addressing

Possible data transfer formats are:

●

Master-transmitter transmits to slave-receiver. The transfer direction is not changed

(see Figure 5 "Master transmit bytes to slave").

●

Master reads slave immediately after first byte (see Figure 5 "Master receive bytes from

slave"). At the moment of the first acknowledge, the master transmitter becomes a

master-receiver and the slave-receiver becomes a slave-transmitter. This first

acknowledge is still generated by the slave. The STOP condition is generated by the

master.

See Figure 6 for the format of first byte after the Start condition.

Figure 6.

First byte after the Start condition

2.2

I2C architecture

In Figure 7 shows the hardware architecture used to implement I2C emulation using the SPI

peripheral.

The ST7MC is connected to the I2C bus through an optoisolator able to isolate the High

voltage section from the bus.

By means of one I/O pin the ST7MC is able to select if the SPI bus is used in I2C emulation

mode or in SPI mode for communication with the SPI Memory. In the first case the

optoisolator is enabled and the SPI memory is disabled, in the second case the optoisolator

is disabled so SPI and I2C are unconnected and SPI memory is enabled.

SLAVE ADDRESS

S

R/W

A

DATA

A

DATA

A

P

SLAVE ADDRESS

S

R/W

A

DATA

A

DATA

A

P

Master transmits bytes to slave

Master receives bytes from slave

From master to slave

From slave to master

‘0’

‘1’

S: Start

P: Stop

A: Acknowledge

Slave address

MSB

LSB

R/W