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UPD6462GS Datasheet(PDF) 31 Page - NEC |
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UPD6462GS Datasheet(HTML) 31 Page - NEC |
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31 / 60 page ![]() 31 µPD6461, 6462 3.8 OUTPUT PIN CONTROL COMMAND This command distributes character signals to the VC1 and VC2 channels (this command is a 2-byte command, requiring 16 bits for each command, even when continuously input). The µPD6461, 6462 support a mask option for selecting one of three formats for the output distribution format for the VC1 and VC2 channels. (1) For MSB-first transfer (Command bits are input starting from the MSB (D15).) D15 1 D14 0 D13 0 D12 1 D11 1 D10 1 D9 0 D8 0 D7 VC2 D6 VC1 D5 0 D4 0 D3 AR3 D2 AR2 D1 AR1 D0 AR0 AR3 0 0 1 AR2 0 0 0 AR1 0 0 1 AR0 0 1 1 VC2 0 0 VC1 0 1 VC2 0 0 VC1 0 1 VC2 0 0 1 1 VC1 0 1 0 1 (MSB) (LSB) Row specification bits Function Specifies row 0. Specifies row 1. Specifies row 11. Other values are invalid. Option A Output pin control bits Output from each pin VC1: Outputs a specified row. VC2: Fixed to low level. VC1: Fixed to low level. VC2: Outputs a specified row. Option B Output pin control bits Output from each pin VC1: Outputs all rows. VC2: Fixed to low level. VC1: Outputs all rows. VC2: Outputs a specified row. Option C Output pin control bits Output from each pin VC1: Outputs columns 0 to 23. VC2: Fixed to low level. VC1: Outputs columns 0 to 11. VC2: Outputs columns 12 to 23. VC1: Outputs columns 12 to 23. VC2: Outputs columns 0 to 11. VC1: Fixed to low level. VC2: Outputs columns 0 to 23. (2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as that for MSB-first transfer.) • Row specification bits Output distribution to the VC1 and VC2 pins is specified for each row (or for 12 columns). These bits are used to specify the row. • Output pin control bits These bits are used to distribute character output signals to the VC1 and VC2 pins depending on whether option A, B, or C has been selected by specifying a mask option (the corresponding blanking signals are output likewise). (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 00111001 AR0 AR1 AR2 AR3 00 VC1 VC2 |
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