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UPD6462GS Datasheet(PDF) 51 Page - NEC |
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UPD6462GS Datasheet(HTML) 51 Page - NEC |
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51 / 60 page  51 µPD6461, 6462 RECOMMENDED OPERATING TIMINGS (TA = –20 to +75 °C, VDD = 2.7 to 5.5 V) Parameter Setup time Hold time Minimum low level width of clock Minimum high level width of clock Clock cycle CS setup time CS hold time Delay from CLK ↑ to CS↑ Minimum low level width of Hsync Minimum low level width of Vsync Conditions Min. 200 200 400 400 1.0 400 400 400 4 4 Typ. Max. Unit ns ns ns ns µs ns ns ns µs µs Symbol tSET tHOLD tCKL tCKH tTCK tCSS tCSH tDCKCS tHWL tVWL DATA CLK CS Hsync Vsync tVWL 10 % tHWL 10 % 10 % 10 % tCSH 90 % tDCKCS 90 % tCSS 10 % tSET tHOLD 90 % 90 % 10 % tCKL tCKH tTCK |
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