AN2555 - Application note

Modified registers

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Accesses to the XPeripherals are configured through 3 pairs of specific XBus configuration registers,

equivalent to the External Bus registers BUSCONx and ADDRSELx. Therefore several XPeripherals are

sharing the same pair, with the consequence that accesses to disabled XPeripherals are only re-directed

to external memory if all the XPeripherals sharing the same pair of registers are disabled.

The XPeripherals are grouped as follows:

●

Group 1: CAN1, CAN2, XASC, XSSC, XI2C, XPWM, XRTC and XMISC, address range 00’E800h-

00’EFFFh.

●

Group 2: XRAM1, address range 00’E000h-00’E7FFh.

●

Group 3: XRAM2 and XFLASH, address range 09’0000h-0F’FFFFh.

3.1.1

Hardware impacts

None.

3.1.2

Software impacts

None if the ST10F269Zx software is not writing to the reserved bit.

3.2

IDCHIP register

A new field has been added inside the IDCHIP register in order to distinguish the different peripheral

options.

ESFR

Reset Value: 10DXh

6

XPWMEN

XPWM Enable

‘0’: Accesses to the XPWM module are disabled, external access performed.

‘1’: The on-chip XPWM module is enabled and can be accessed.

7

XASCEN

XASC Enable Bit

‘0’: Accesses to the XASC module are disabled, external access performed.

‘1’: The on-chip XASC is enabled and can be accessed.

8

XSSCEN

XSSC Enable Bit

‘0’: Accesses to the XSSC module are disabled, external access performed.

‘1’: The on-chip XSSC is enabled and can be accessed.

9XI2CEN

XI 2 C Enable Bit

‘0’: Accesses to the XI2C module are disabled, external access performed.

‘1’: The on-chip XI 2 C is enabled and can be accessed.

10

XMISCEN

XBUS Additional Features Enable Bit

‘0’: Accesses to the Additional Miscellaneous Features are disabled.

‘1’: The Additional Features are enabled and can be accessed.

11...15

Reserved

15

14

13

12

11

10

9876543210

CHIPID

REVID

RR

Bit

number

Bit name

Function