AN4031 datasheet(11/36 Pages) STMICROELECTRONICS

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AN4031

DMA controller description

1.1.5

Transfer size

The transfer size value has to be defined only when the DMA is the flow controller. In fact,

this value defines the volume of data to be transferred from source to destination.

The transfer size is defined by the DMA_SxNDTR register value and by the peripheral side

data width. Depending on the received request (burst or single), the transfer size value is

decreased by the amount of the transferred data.

1.1.6

Incrementing source/destination address

It is possible to configure the DMA to automatically increment the source and/or destination

address after each data transfer.

Figure 3. DMA source address and destination address incrementing

1.1.7

Source and destination data width

Data width for source and destination can be defined as:

●

Byte (8 bits)

●

Half-word (16 bits)

●

Word (32 bits)

1.1.8

Transfer types

•

Circular mode: the Circular mode is available to handle circular buffers and continuous

data flows (the DMA_SxNDTR register is then reloaded automatically with the

previously programmed value).

•

Normal mode: once the DMA_SxNDTR register reaches zero, the stream is disabled

(the EN bit in the DMA_SxCR register is then equal to 0).

1.1.9

DMA FIFO mode

Each stream has an independent 4-word (4 * 32 bits) FIFO and the threshold level is

software-configurable between 1/4, 1/2, 3/4 or full. The FIFO is used to temporarily store

data coming from the source before transmitting them to the destination.

DMA FIFO can be enabled or disabled by software; when disabled, the Direct mode is used.

If DMA FIFO is enabled, data packing/unpacking and/or Burst mode can be used. The

configured DMA FIFO threshold defines the DMA memory port request time.

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