AN4031 datasheet(31/36 Pages) STMICROELECTRONICS

Part #	AN4031

Description	Using the STM32F2 and STM32F4 DMA controller

PDF	36 Pages

Scroll/Zoom	100%

Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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31 / 36 page

DocID022648 Rev 1

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AN4031

How to predict DMA latencies

This figure illustrates the following conclusions:

•

CPU polling on APB1 is not impacting the DMA transfer latency on APB2.

•

For the DMA2_Stream2 (SPI1_RX) transaction, at the eighth AHB clock cycle, there is

no bus matrix arbitration since it is supposed that the last master that accessed the

SRAM is DMA2 (so no re-arbitration is needed).

•

For the DMA2_Stream3 (SPI1_TX) transaction, this stream anticipates the read from

SRAM and writes it on the FIFO and then, once triggered, the DMA peripheral port

(destination is SPI1) starts operation.

•

For DMA2_Stream3, the DMA peripheral arbitration phase (1 AHB cycle) is executed

during the DMA2_Stream2 bus synchronization cycle.

This optimization is always executed like this when the DMA request is triggered before

the end of a current DMA request transaction.

AN4031 Datasheet(PDF) 31 Page - STMicroelectronics