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RM0312 Datasheet(PDF) 59 Page - STMicroelectronics |
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RM0312 Datasheet(HTML) 59 Page - STMicroelectronics |
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59 / 275 page  DocID022352 Rev 3 59/275 RM0312 Reset (RST) and voltage detection 74 7.4 RST registers 7.4.1 Reset pin configuration register (RST_CR) Address offset: 0x00 Reset value: 0x00 7.4.2 Reset status register (RST_SR) Address offset: 0x01 Reset value after power-on reset: 0x01 Note: RST_SR reset value depends on the previous reset source. 7 654 3210 RSTPIN_KEY rwo Bits 7:0 RSTPIN_KEY[7:0]: Reset pin configuration key 0x00: NRST/PA5 configured as reset pin (default reset value) 0xD0: NRST/PA5 configured as general purpose output These bits are write once only. They can also be read at any time. Note: Writing any value beside D0h is equivalent to writing 00h. 7 654 3210 Reserved WWDGF SWIMF ILLOPF IWDGF PORF rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 7:5 Reserved Bit 4 WWDGF: Window Watchdog reset flag 0: No WWDG reset occurred 1: A WWDG reset occurred This bit is set by hardware and cleared by software writing “1”. Bit 3 SWIMF: SWIM reset flag 0: No SWIM reset occurred 1: A SWIM reset occurred This bit is set by hardware and cleared by software writing “1”. Bit 2 ILLOPF: Illegal opcode reset flag 0: No ILLOP reset occurred 1: An ILLOP reset occurred This bit is set by hardware and cleared by software writing “1”. Bit 1 IWDGF: Independent Watchdog reset flag 0: No IWDG reset occurred 1: An IWDG reset occurred This bit is set by hardware and cleared by software writing “1”. Bit 0 PORF: Power-on reset (POR) flag 0: No POR occurred 1: A POR occurred This bit is set by hardware and cleared by software writing “1”. |
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