RM0312 datasheet(63/275 Pages) STMICROELECTRONICS

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RM0312

Clock control (CLK)

8.2

LSI clock

The LSI RC oscillator generates the fLSI clock. This clock is a 38-kHz Low Speed Internal

RC oscillator (LSI RC). It is used by the independent watchdog (IWDG), Auto-Wakeup unit

(AWU) and beeper (BEEP). The LSI is active in Active-halt mode and can be kept in run

mode.

8.3

Configurable clock-output capability (CCO)

The configurable clock output (CCO) capability outputs a clock on the external CLK_CCO

pin. The master clock is used to drive the clock output with a programmable prescaler which

can divide the clock frequency by a factor of 1, 2, 4 or 16.

The selection is controlled by the CCOSEL[2:0] bits in the Configurable clock output register

(CLK_CCOR).

The sequence to output the targeted clock starts with CCOEN=1 in Configurable clock

output register (CLK_CCOR). When CCOEN=1, the CCOSEL[2:0] bits are write protected.

To disable the clock output the user has to clear the CCOEN bit.

The configurable clock output has a configurable slope which must be adapted according to

the output frequency. It is recommended to select a buffer slope at least twice that of the

targeted output frequency.

8.4

CLK registers

8.4.1

Clock divider register (CLK_CKDIVR)

Address offset: 0x00

Reset value: 0x03

654

3210

Reserved

HSIDIV[1:0]

Bits 7:2 Reserved

Bits 1:0 HSIDIV[1:0]: High speed internal clock prescaler

00: fMASTER= fHSI RC output

01: fMASTER= fHSI RC output/2

10: fMASTER= fHSI RC output/4

11: fMASTER= fHSI RC output/8

These bits are written by software to define the HSIDIV prescaling factor.

RM0312 Datasheet(PDF) 63 Page - STMicroelectronics