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LT4254 Datasheet(PDF) 13 Page - Linear Technology

Part # LT4254
Description  Positive High Voltage Hot Swap Controller with Open-Circuit Detect
PDF  16 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LT4254 Datasheet(HTML) 13 Page - Linear Technology

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LT4254
13
4254fb
LT4254 stays in current limit long enough for the TIMER
pin to fully charge up to its threshold, the LT4254 will
either latch off (RETRY = 0) or go into the current limit
hiccup mode (RETRY = floating). In either case, an open
FET condition will be falsely signalled. If the LT4254 does
go into current limit during start-up, C1 can be increased
(see Power-Up Sequence).
Supply Transient Protection
The LT4254 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 44V. However,
voltage transients above 44V may damage the part.
During a short-circuit condition, the large change in
currents flowing through the power supply traces can
cause inductive voltage transients which could exceed
44V. To minimize the voltage transients, the power trace
parasitic inductance should be minimized by using wider
traces or heavier trace plating and a 0.1
µF bypass capaci-
tor should be placed between VCC and GND. A surge
APPLICATIO S I FOR ATIO
suppressor (Transorb) at the input can also prevent
damage from voltage transients.
GATE Pin
A curve of gate drive vs VCC is shown in Figure 13. The
GATE pin is clamped to a maximum voltage of 12V above
the VCC voltage. This clamp is designed to withstand the
internal charge pump current. An external zener diode
should be used if the possibility exists for an instanta-
neous low resistance short on VOUT to occur. At a mini-
mum input supply voltage of 12V, the minimum gate drive
voltage is 4.5V. When the input supply voltage is higher
than 20V, the gate drive voltage is at least 10V and a
Figure 11. Active Low Enable PWRGD Application
4254 F11
R5
100m
Ω
LT4254
SENSE
13
10
5
7
8
16
15
1
2
4
9
VCC
GATE
FB
PWRGD
RETRY
UV
OV
TIMER
GND
VCC
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R3
40.2k
R2
40.2k
R1
324k
R7
100
Ω
R6
10
Ω
VOUT
VLOGIC
R4
27k
R8
140k
CL
R10
27k
C2
33nF
C3
0.1
µF
C1
10nF
OPEN
UV = 20V
OV = 40V
PWRGD = 18V
R9
40.2k
Q2
PWRGD
GND
Figure 12. Delay Circuit for OPEN FET Detection
4
R
C
4254 F12
OPEN
LT4254
TO
MONITORING
LOGIC
VLOGIC
INTERNAL
OPEN COLLECTOR
PULL-DOWN
Figure 13.
∆VGATE vs VCC
VCC (V)
10
8
9
10
4254 F13
7
6
4
20
30
40
5
12
11
∆VGATE = VGATE – VCC



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