AN4088 datasheet(38/71 Pages) STMICROELECTRONICS

38 / 71 page

Peripheral migration

AN4088

38/71

DocID023072 Rev 3

3.16

CEC interface

The STM32F0 series embeds a new CEC peripheral versus the STM32F1 series. The

architecture, features and programming interface are modified to introduce new capabilities.

As a consequence, the STM32F0 CEC programming procedures and registers are different

from those of the STM32F1 series, so any code written for the STM32F1 series using the

CEC needs to be rewritten to run on STM32F0 series.

The STM32F0 CEC provides best-in-class added features:



32 KHz CEC kernel with dual clock

–

LSE

–

HSI/244



Reception in listen mode



Rx tolerance margin: standard or extended



Arbitration (signal free time): standard (by H/W) or aggressive (by S/W)



Arbitration lost detected flag/interrupt



Automatic transmission retry supported in case of arbitration lost



Multi-address configuration



Wake-up from STOP mode



Receive error detection

–

Bit rising error (with stop reception)

–

Short bit period error

–

Long bit period error



Configurable error bit generation

–

on bit rising error detection

–

on long bit period error detection



Transmission under run detection



Reception overrun detection

The following features present in the STM32F1 family are now handled by the new

STM32F0 CEC features and thus are no more available.



Bit timing error mode & bit period error mode, by the new error handler



Configurable prescaler frequency divider, by the CEC fixed kernel clock

For more information about STM32F0 CEC features, please refer to CEC chapter of

STM32F0xx Reference Manual (RM0091).

AN4088 Datasheet(PDF) 38 Page - STMicroelectronics

AN4088 Datasheet(HTML) 38 Page - STMicroelectronics

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