UPD750004A datasheet(55/84 Pages) NEC

55 / 84 page

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Recommended

constant

Resonator

Parameter

kHz

µs

Unit

Max.

Typ.

Min.

100

32.768

1.0

Conditions

Crystal

External

clock

XT1

XT2

Oscillator frequency (fXT)Note 1

Oscillation settling timeNote 2

XT1 input frequency (fXT)Note 1

XT1 input high/low level width

(tXTH, tXTL)

VDD = 2.2 to 5.5 V

VDD = 4.5 to 5.5 V

VDD = 2.2 to 5.5 V

VDD = 1.8 to 5.5 V

CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (TA = -40 to +85

°C)

Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of

AC characteristics for the instruction execution time.

2. The oscillation settling time means the time required for the oscillation to settle after VDD is applied.

Caution When the subsystem clock oscillator is used, conform to the following guidelines when wiring at

the portions of surrounded by dotted lines in the figures above to eliminate the influence of the

wiring capacity.

• The wiring must be as short as possible.

• Other signal lines must not run in these areas.

• Any line carrying a high fluctuating current must be kept away as far as possible.

• The grounding point of the capacitor of the oscillator must have the same potential as that of VSS

• It must not be grounded to ground patterns carrying a large current.

• No signal must be taken from the oscillator.

When the subsystem clock is used, pay special attention to its wiring; the subsystem clock

oscillator has low amplification to minimize current consumption and is more likely to malfunction

due to noise than the main system clock oscillator.

XT1

XT2

UPD750004A Datasheet(PDF) 55 Page - NEC

UPD750004A Datasheet(HTML) 55 Page - NEC

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