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UPD750004A Datasheet(PDF) 17 Page - NEC |
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UPD750004A Datasheet(HTML) 17 Page - NEC |
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17 / 84 page ![]() 17 µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Fig. 5-1 Program Memory Map (in µPD750004) Note Can be used only in the Mk ΙΙ mode. Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the 8 low-order bits of the PC changed. 000H Address 765 4 MBE RBE 0 0 Internal reset start address (high-order 4 bits) 0 002H MBE RBE 0 0 INTBT/INT4 (high-order 4 bits) start address 004H MBE RBE 0 0 INT0 (high-order 4 bits) start address 006H MBE RBE 0 0 INT1 (high-order 4 bits) start address 008H MBE RBE 0 0 INTCSI (high-order 4 bits) start address 00AH MBE RBE 0 0 INTT0 (high-order 4 bits) start address 00CH MBE RBE 0 0 INTT1 (high-order 4 bits) start address 020H 07FH 080H 7FFH 800H FFFH GETI instruction reference table (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) (low-order 8 bits) CALLF ! faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address BRCB !caddr instruction branch address -15 to -1, +2 to +16 Branch destination address and subroutine entry address when GETI instruction is executed Internal reset start address INTBT/INT4 start address INT0 start address INT1 start address INTCSI start address INTT0 start address INTT1 start address |
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