UPD750004A datasheet(14/84 Pages) NEC

14 / 84 page

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

4. Mk

Ι MODE/Mk ΙΙ MODE SWITCH FUNCTION

4.1

DIFFERENCES BETWEEN Mk

Ι MODE AND Mk ΙΙ MODE

The CPU of the

µPD750008 has two modes (Mk Ι mode and Mk ΙΙ mode) and which mode is used is selectable.

Bit 3 of the stack bank selection register (SBS) determines the mode.

• Mk

Ι mode:

This mode has the upward compatibility with the

µPD75008.

It can be used in the 75XL CPUs having a ROM of up to 16 KB.

• Mk

ΙΙ mode: This mode is not compatible with the

µPD75008.

It can be used in all 75XL CPUs, including those having a ROM of 16 KB or more.

Table 4-1 shows the differences between Mk

Ι mode and Mk ΙΙ mode.

Table 4-1

Differences between Mk

Ι Mode and Mk ΙΙ Mode

Caution Mk

ΙΙ mode can be used to support a program area larger than 16K bytes in the 75X series or 75XL

series. This mode enhances a software compatibility with products whose program area is larger

than 16K bytes. In Mk

ΙΙ mode, one more stack byte is required for execution of subroutine call

instructions per stack compared with Mk

Ι mode. When a CALL !addr or CALLF !faddr instruction

is executed, it takes one more machine cycle. Therefore, Mk

Ι mode should be used for applications

for which RAM efficiency or processing capabilities is more critical than a software compatibility.

Number of stack bytes in a

subroutine instruction

BRA !addr1 instruction

CALLA !addr1 instruction

CALL !addr instruction

CALLF !faddr instruction

2 bytes

None

3 machine cycles

2 machine cycles

3 bytes

Available

4 machine cycles

3 machine cycles

Ι mode

ΙΙ mode

UPD750004A Datasheet(PDF) 14 Page - NEC

UPD750004A Datasheet(HTML) 14 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Datasheet Download

Link URL