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LT1910 Datasheet(PDF) 7 Page - Linear Technology |
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LT1910 Datasheet(HTML) 7 Page - Linear Technology |
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7 / 14 page ![]() LT1910 7 1910fb For more information www.linear.com/LT1910 operaTion also activates the open-collector NPN to pull the FAULT pin LOW, indicating an overcurrent condition. When the MOSFET gate voltage is discharged to less than 1.4V, the TIMER pin is released. The 14µA current source then slowly charges the timing capacitor back to 2.9V where the charge pump again starts to drive the GATE pin HIGH. If a fault condition still exists, the sense comparator threshold will again be exceeded and the timer cycle will repeat until the fault is removed. The FAULT pin becomes inactive HIGH if the TIMER pin charges up successfully above 3.4V (see Figure 1). 3.4V 1910 F01 0V GATE TIMER FAULT IN OVERCURRENT NORMAL NORMAL OFF 0V 0V 0V 5V 3.5V 2.9V V+ 12V Figure 1. Timing Diagram applicaTions inFormaTion Input/Supply Sequencing There are no input/supply sequencing requirements for the LT1910. The IN pin may be taken up to 15V with the supply at 0V. When the supply is turned on with the IN pin set HIGH, the MOSFET turn-on will be inhibited until the timing capacitor charges up to 2.9V (i.e., for one restart cycle). Isolating the Inputs Operation in harsh environments may require isolation to prevent ground transients from damaging control logic. TheLT1910easilyinterfacestolowcostoptoisolators.The network shown in Figure 2 ensures that the input will be pulled above 2V, but not exceed the absolute maximum rating for supply voltages of 12V to 48V over the entire temperature range. The optoisolator must have less than 20µA of dark current (leakage) at hot in order to maintain the off state (see Figure 2). Drain-Sense Configuration The LT1910 uses supply referenced current sensing. One input of the current-sense comparator is connected to a drain-sense pin, while the second input is offset 65mV below the supply inside the device. For this reason, Pin 8 of the LT1910 must be treated not only as a supply pin, but also as the reference input for the current-sense comparator. Figure 3 shows the proper drain-sense configuration for the LT1910. Note that the SENSE pin goes to the drain end of the sense resistor, while the V+ pin is connected IN 51k 100k 2k LOGIC INPUT 12V TO 48V LT1910 GND POWER GROUND LOGIC GROUND 1 1910 F02 4 FAULT IN TIMER V+ SENSE GATE 3 4 2 8 6 5 LT1910 R1 5.1k 24V 5V FAULT OUTPUT INPUT 0V GND Q1 IRFZ34 24V 2A SOLENOID 1910 F03 C1 100µF 50V CT 1µF 1 RS 0.02 (PTC) + Figure 2. Isolating the Input Figure 3. Drain-Sense Configuration |
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