UPD75206 datasheet(49/62 Pages) NEC

49 / 62 page

µPD75206

2.0

6.0

VDDDR = 2.0V

0.1

µA

µs

Release by RESET

217/fX

Release by interrupt request

DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40

to +85

°C)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Data retention power

supply voltage

Data retention power

supply current *1

tSREL

tWAIT

VDDDR

IDDDR

Release signal set time

Oscillation stabilization

wait time *2

Data Retention Timing (STOP Mode Release by RESET)

STOP Instruction Execution

VDD

VDDDR

Operating Mode

HALT Mode

STOP Mode

Data Retention Mode

tWAIT

RESET

tSREL

Internal Reset Operation

BTM3

BTM2

BTM1

BTM0

Wait Time (Values at fXX = 4.19 MHz in parentheses)

—0

220/fX (approx. 250 ms)

—0

217/fX (approx. 31.3 ms)

—1

215/fX (approx. 7.82 ms)

—1

213/fX (approx. 1.95 ms)

*1. Current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included.

2. Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation

start.

3. According to the setting of the basic interval timer mode register (BTM) (see below).

UPD75206 Datasheet(PDF) 49 Page - NEC

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