UPD754202GS datasheet(12/66 Pages) NEC

12 / 66 page

µPD754202, 754202(A)

SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE

4.1 Differences between Mk I Mode and Mk II Mode

The

µPD754202 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The

mode can be switched by bit 3 of the stack bank select register (SBS).

• Mk I mode :

Instructions are compatible with the 75X Series. Can be used in the 75XL CPU with a ROM

capacity of up to 16 Kbytes.

• Mk II mode:

Incompatible with 75X Series. Can be used in all the 75XL CPU’s including those products

whose ROM capacity is more than 16 Kbytes.

Table 4-1. Differences between Mk I Mode and Mk II Mode

Mk I mode

Mk II mode

Number of stack bytes

2 bytes

3 bytes

for subroutine instructions

BRA !addr1 instruction

Not available

Available

CALLA !addr1 instruction

CALL !addr instruction

3 machine cycles

4 machine cycles

CALLF !faddr instruction

2 machine cycles

3 machine cycles

Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL

Series. Therefore, this mode is effective for enhancing software compatibility with

products that have a program area of more than 16 Kbytes.

The number of stack bytes (usable area) during execution of subroutine call instruc-

tions increases by 1 byte per stack compared to the Mk I mode when the Mk II mode

is selected.

However, when the CALL !addr and CALL !faddr instructions are used, the machine

cycle becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on

RAM use efficiency and processing performance than on software compatibility, the

Mk I mode should be used.

UPD754202GS Datasheet(PDF) 12 Page - NEC